The present invention relates to bootstrap circuits and more particularly to a circuit which can receive two clock signals and provide corresponding booted clock signals out on a single output line in response to control signals. In semiconductor devices, clock generators are employed which have output driver circuits for driving capacitive loads between a low level, usually ground, and high level, usually the supply voltage. In driving towards the high level using MOS devices, there is encountered a voltage drop of one enhancement threshhold voltage from the supply voltage which is caused by the electrical characteristics of MOS devices. The clocking signal thereby loses some of its amplitude causing deterioration in the operation of circuits which are activated by the clock signal. Bootstrap circuits are used to increase and/or restore the full amplitude of the clock signal. In integrated circuit design, the area required for conductors and devices limits the reduction in size of the chip on which the circuit is implemented and in turn increases the cost and generally decreases the speed of the circuit. It is therefor desirable, if possible, to run two signals over the same line, thereby eliminating the need for one line as long as the two signals do not interfere with each other. Such being the case, the area required to implement a circuit is reduced making for smaller and faster circuits. The present circuit seeks to achieve these advantages when non-overlapping clock signals have to be booted.
Some patents of interest for showing the state of the art for bootstrapping circuits are U.S. Pat. No. 4,352,996 entitled "IGFET Clock Generator Circuit Employing MOS Bootstrap Capacitive Drive" by L. S. White, Jr.; U.S. Pat. No. 4,431,927 entitled "MOS Capacitive Bootstrapping Trigger Circuit for a Clock Generator" by S. S. Eaton, Jr. et al.; and U.S. Pat. No. 4,443,720 entitled "Bootstrap Circuit" by Y. Takemae.